verilog串口代码

verilog串口代码，本模块包含有FIFO功能，可以对串口数据进行连续读写，并且不会丢失数据，FPGA串口读到数据之后直接再发送出来，在串口调试助手中可以进行显示。

uart_fifo_design
src
fifo_uart.bsf
fifo_uart.qip
fifo_uart.v
fifo_uart_bb.v
fifo_uart_wave0.jpg
fifo_uart_wave1.jpg
fifo_uart_waveforms.html
uart_fifo_design.asm.rpt
uart_fifo_design.cdf
uart_fifo_design.done
uart_fifo_design.dpf
uart_fifo_design.fit.rpt
uart_fifo_design.fit.smsg
uart_fifo_design.fit.summary
uart_fifo_design.flow.rpt
uart_fifo_design.map.rpt
uart_fifo_design.map.summary
uart_fifo_design.pin
uart_fifo_design.pof
uart_fifo_design.qpf
uart_fifo_design.qsf
uart_fifo_design.qws
uart_fifo_design.sim.rpt
uart_fifo_design.sof
uart_fifo_design.sta.rpt
uart_fifo_design.sta.summary
uart_fifo_design.tan.rpt
uart_fifo_design.tan.summary
uart_fifo_design.tcl
uart_fifo_design.tcl.bak
uart_fifo_design.vwf