verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过...

verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through

ALDEC.INI
ALDEC.LOG
BTI.INI
CALCULAT.PDF
CALCULAT
ADDER.ALR
ADDER.ASX
ADDER.BAK
ADDER.EDF
ADDER.ER
ADDER.LOG
ADDER.OPT
ADDER.V
CALCULA1.BSC
CALCULA1.ERR
CALCULA1.SCH
CALCULAT.ALB
CALCULAT.BIT
CALCULAT.EDN
CALCULAT.LL
CALCULAT.PRJ
CALCULAT.TVE
CALCULAT.UCF
DECODER10TO7.ALR
DECODER10TO7.ASX
DECODER10TO7.EDF
DECODER10TO7.ER
DECODER10TO7.LOG
DECODER10TO7.OPT
DECODER10TO7.V
DPMCOMP.TMP
CHIPS
ADDER
ADDER.CST
ERRLOG.LOG
EXP_EDIF.LOG
FREQDIVIDE.ALR
FREQDIVIDE.ASX
FREQDIVIDE.EDF
FREQDIVIDE.ER
FREQDIVIDE.LOG
FREQDIVIDE.OPT
FREQDIVIDE.V
IMP_EDIF.LOG
LIB
CALCULAT.BLK
MERGE.ALR
MERGE.ASX
MERGE.BAK
MERGE.EDF
MERGE.ER
MERGE.LOG
MERGE.OPT
MERGE.V
NETLIST.LOG
S95.LOG
SCAN.ALR
SCAN.ASX
SCAN.BAK
SCAN.EDF
SCAN.ER
SCAN.LOG
SCAN.OPT
SCAN.V
SELECTOR.ALR
SELECTOR.ASX
SELECTOR.BAK
SELECTOR.EDF
SELECTOR.ER
SELECTOR.LOG
SELECTOR.OPT
SELECTOR.V
TIME_SIM.EDN
TYPES.DIR
VHDL.LST
XPROJ.INI
XPROJ
CALCULAT.XPJ
CURRENT.PDF