一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考...
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一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference
文 件 列 表
100vhdl例子
TEMP
workdirs
94_SPARC
93_WSS
92_WSS
91_WSS
90_WSS
9_MVL7_TYPES
89_full_adder
88_arms_counter
87_control
86_STACK
85_UPC
84_REG
83_multiplexer
82_output_shifter
81_Q_REG
80_MEM
8_BITPKG
79_ALU
78_alu_input
77_NPS
76_PID
75_RAM
74_alarm_clock
73_alarm_fq
72_alarm_display
71_alarm_counter
70_alarm_buffer
7_shiftreg
69_decoder
68_alarm_controller
67_ellipf
66_FIR
65_conditioner
64_TLC
63_gcd_disp
62_GCD
61_assign
6_REG
59_decoder
58_decoder
57_instruction_dec
56_prefetch
55_falsepath
54_display
53_counter
52_divider
51_test_113
50_test_18e
5_MUX2
49_DELTA
48_test_18e
47_CONST
46_generic
45_test_63
44_reg_counter
43_register
42_MIX
41_generic_testbench
40_generic_dec
4_COMP
39_wst0dp
38_test_28
37_test_105
36_GCD
35_486_bus
34_BUS
33_comparer
32_test_110b
31_test_35b
30_test_3
3_MUL
29_test_35
28_test_64a
27_test_16
26_test_74s
25_test_1
24_test_195
23_test_120
22_deadlock
21_test_13a
20_test_159
2_ADDER
19_test_194
18_LIB
17_parity
16_MUX
15_MUX41
14_MVL7_functions
13_SHL
12_convert
11_wiredor
10_function
1_ADDER
a.lsq
temp文件夹不需要，可是删不掉了.txt
TEMP
workdirs
WORK
