source for VLSI systems design project spring 2009 at university of Cincinnati

20-EECE-681—Quarter Project April 1, 2009 Your overall goal for this quarter is to design and implement on the provided Altera boards an "optimal" processor. Parameters for optimization include speed, size, power usage, and potential for upgrading with wider datapath, more instructions, etc. The processor will be designed in three phases. Your processor must have the following characteristics: Phase 1: --8 or 16 bit datapath --maximal clock speed --input may be through a preloaded data file, along with a menu on the CRT which is accessed through the mouse --output may be to a file which can be displayed appropriately on the CRT --ability to execute 4 benchmark programs: a. mergesort of a list of integers b. quicksort of the same list c. matrix multiplication d. fast Fourier transform Phase II: add pipelining Phase III: add a second processor and memory manage