Verilog HDL 4bit_processor
资 源 简 介
RTL码由控制、alu、寄存器、keych模块等组成。。。
文 件 列 表
alu
ALU.v
ALU.v.bak
ALU.v~
acc+alu.v~
acc_alu.v
acc_alu.v.bak
acc_alu.v~
tb_add_ALU.v.bak
tb_add_ALU.v~
tb_add_sub_ALU.v.bak
tb_add_sub_ALU.v~
tb_add_sub_and_ALU.v
tb_div_ALU.v
tb_div_ALU.v.bak
tb_div_ALU.v~
tb_mul_ALU.v
tmp_acc.v
tmp_acc.v.bak
tmp_acc.v~
control
Ring_counter.v
Ring_counter.v.bak
Ring_counter.v~
TOP_control.v
TOP_control.v~
control_logic.v
control_logic.v.bak
control_logic.v~
decoder.v
decoder.v~
tb_control_logic.v
tb_control_logic.v.bak
tb_control_logic.v~
tb_ring.v
tb_ring.v.bak
input
TOP_input.v
TOP_input.v.bak
debounce.v
debounce.v~
debounce~
encoder.v
encoder.v.bak
encoder.v~
tb_input.v
tb_input.v.bak
tb_input.v~
register
ACC_register.v
ACC_register.v.bak
ACC_register.v~
PC_reg.v
PC_reg.v~
TOP_reg.v
TOP_reg.v~
bit4_register_1ic.v
bit4_register_1ic.v~
bit4_register_1oc.v
bit4_register_1oc.v~
bit4_register_2c.v
bit4_register_2c.v~
bit8_register_1ic.v
bit8_register_1ic.v~
bit8_register_1oc.v~
bit8_register_2c.v
bit8_register_2c.v~
keych_register.v
keych_register.v~
tb_4bit_1ic.v
tb_4bit_1ic.v~
tb_4bit_1oc.v
tb_4bit_1oc.v.bak
tb_4bit_2c.v
tb_4bit_2c.v~
tb_8bit_1ic.v
tb_8bit_1ic.v~
tb_8bit_2c.v
tb_ACC.v
tb_ACC.v.bak
tb_PC.v
tb_PC.v.bak
tb_keych.v
tb_keych.v.bak
TOP
TOP.v
TOP.v~
