一位十进制可逆计数器的Verilog代码

Verilog实现的一位十进制可逆计数器，可以实现十进制数的加减功能，有仿真图，计数器模数为10，有计数器使能控制，进位输出，具有同步置数和异步清零功能

simulation
qsim
modelsim
output_files
T5_2.asm.rpt
T5_2.done
T5_2.eda.rpt
T5_2.fit.rpt
T5_2.fit.smsg
T5_2.fit.summary
T5_2.flow.rpt
T5_2.jdi
T5_2.map.rpt
T5_2.map.summary
T5_2.pin
T5_2.pof
T5_2.sim.rpt
T5_2.sof
T5_2.sta.rpt
T5_2.sta.summary
incremental_db
compiled_partitions
README
db
logic_util_heursitic.dat
prev_cmp_T5_2.qmsg
T5_2.(0).cnf.cdb
T5_2.(0).cnf.hdb
T5_2.asm.qmsg
T5_2.asm.rdb
T5_2.asm_labs.ddb
T5_2.cbx.xml
T5_2.cmp.bpm
T5_2.cmp.cdb
T5_2.cmp.hdb
T5_2.cmp.idb
T5_2.cmp.kpt
T5_2.cmp.logdb
T5_2.cmp.rdb
T5_2.cmp0.ddb
T5_2.cmp1.ddb
T5_2.cmp2.ddb
T5_2.cmp_merge.kpt
T5_2.db_info
T5_2.eda.qmsg
T5_2.eds_overflow
T5_2.fit.qmsg
T5_2.fnsim.hdb
T5_2.fnsim.qmsg
T5_2.hier_info
T5_2.hif
T5_2.ipinfo
T5_2.lpc.html
T5_2.lpc.rdb
T5_2.lpc.txt
T5_2.map.ammdb
T5_2.map.bpm
T5_2.map.cdb
T5_2.map.hdb
T5_2.map.kpt
T5_2.map.logdb
T5_2.map.qmsg
T5_2.map.rdb
T5_2.map_bb.cdb
T5_2.map_bb.hdb
T5_2.map_bb.logdb
T5_2.pplq.rdb
T5_2.pre_map.hdb
T5_2.pti_db_list.ddb
T5_2.root_partition.map.reg_db.cdb
T5_2.routing.rdb
T5_2.rtlv.hdb
T5_2.rtlv_sg.cdb
T5_2.rtlv_sg_swap.cdb
T5_2.sgdiff.cdb
T5_2.sgdiff.hdb
T5_2.sim.hdb
T5_2.sim.qmsg
T5_2.sim.rdb
T5_2.sim.vwf
T5_2.simfam
T5_2.sld_design_entry.sci
T5_2.sld_design_entry_dsc.sci
T5_2.smart_action.txt
T5_2.sta.qmsg
T5_2.sta.rdb
T5_2.sta_cmp.8_slow.tdb
T5_2.syn_hier_info
T5_2.tis_db_list.ddb
T5_2.tmw_info
T5_2.vpr.ammdb
T5_2.v
T5_2.v.bak
T5_2_description.txt
Waveform.vwf
Waveform1.vwf
Waveform1.vwf.temp
T5_2.qpf
T5_2.qsf
T5_2.qws