PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过...

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

pll
aa.gdf
edge.acf
edge.cnf
edge.fit
edge.gdf
edge.hex
edge.hif
edge.mmf
edge.ndb
edge.pin
edge.pof
edge.rpt
edge.scf
edge.snf
edge.sof
edge.ttf
inst1.gdf
mealy1.acf
mealy1.cnf
mealy1.fit
mealy1.gdf
mealy1.hex
mealy1.hif
mealy1.mmf
mealy1.ndb
mealy1.pin
mealy1.pof
mealy1.rpt
mealy1.scf
mealy1.snf
mealy1.sof
mealy1.ttf
pll(1).cnf
pll(2).cnf
pll(3).cnf
pll(4).cnf
pll(5).cnf
pll.acf
pll.cnf
pll.fit
pll.gdf
pll.hif
pll.jam
pll.jbc
pll.mmf
pll.ndb
pll.pin
pll.pof
pll.rpt
pll.scf
pll.snf
pll1(1).cnf
pll1(2).cnf
pll1(3).cnf
pll1(4).cnf
pll1.acf
pll1.cnf
pll1.fit
pll1.gdf
pll1.hif
pll1.jam
pll1.jbc
pll1.mmf
pll1.ndb
pll1.pin
pll1.pof
pll1.rpt
pll1.snf
read me.txt