Verilog realize the DDS sine wave signal generator and frequency measurement mod...
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资 源 简 介
Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
文 件 列 表
WorkOneBetaC
timing
simulation
db
Adjust.v
Accumulater.v
Adapter.v
Adjust.v.bak
DDS.v
FreFindTable.v
FreFindTable_bb.v
Measure.v
PhaseFindTable.v
PhaseFindTable_bb.v
Read.v.bak
SinFindTable.v
SinFindTable_bb.v
Strobe.v
WorkOneBeta.qpf
WorkOneBeta.qsf
WorkOneBeta_description.txt
WorkOneBeta.fit.rpt
Measure.v.bak
Measure.bsf
WorkOneBeta.done
WorkOneBeta.flow.rpt
Read.v
WorkOneBeta.map.smsg
WorkOneBeta.map.summary
WorkOneBeta.asm.rpt
WorkOneBeta.tan.rpt
Sin_12b.mif
Degree.mif
Hz.mif
WorkOneBeta.pin
WorkOneBeta.fit.smsg
WorkOneBeta.fit.summary
WorkOneBeta.eda.rpt
WorkOneBeta.sof
WorkOneBeta.pof
prev_cmp_WorkOneBeta.qmsg
WorkOneBeta.tan.summary
WorkOneBeta.map.rpt
WorkOne.v.bak
PLL.ppf
WorkOneBeta.dpf
WorkOneBeta.cdf
WorkOneBeta.vwf
WorkOneBeta.sim.rpt
Read.bsf
WorkOne.v
Strobe.v.bak
PLL_waveforms.html
PLL_wave0.jpg
Adjust.bsf
PLL.v
PLL_bb.v
Strobe.bsf
Accumulater.v.bak
PLL.bsf
