设计与验证Verilog_实例，经典的HDl书籍，强烈推荐

设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend

Example-8-2
NonBlocking_LHS_Delay
Blocking_RHS_Delay
Blocking_LHS_Delay
NonBlocking_RHS_Delay
sim.do
示例说明.doc
NonBlocking_RHS_Delay
Example-8-1
sim
INV_DFF.v
示例说明.doc
sim
Example-7-4
Proj
altera_mf.v
示例说明.doc
Proj
Example-7-3
Proj
altera_mf.v
示例说明.doc
Example-7-2
Proj
altera_mf.v
示例说明.doc
Example-7-1
Proj
altera_mf.v
示例说明.doc
Example-6-1
FSM
state_default
rev_2
示例说明.doc
FSM
state_default
rev_2
syntmp
syntmp
Example-5-8
rev_2
verif
shannon.prd
shannon.prj
source
shannon_fast.v
示例说明.doc
source
Example-5-7
rev_1
syntmp
mod_copy.prd
mod_copy.prj
source
mod_copy1.v
示例说明.doc
Example-5-6
rev_1
verif
resource_share.prd
resource_share.prj
source
resource_share1.v
示例说明.doc
Example-5-5
rev_2
verif
latch.prd
latch.prj
latch.v
source
latch.v
syntmp.msg
示例说明.doc
Example-5-1
soure
after_optimized
before_optimized
rev_1
syntmp
FHTPART_resource.bmp
FHTPART_resource.gif
Thumbs.db
wchfht_resource.bmp
wchfht_resource.gif
workspace_VS.prd
workspace_VS.prj
示例说明.doc
soure
before_optimized
Example-4-8
sim
work
_info
rev_2
syntmp
decode_cmb.prd
decode_cmb.prj
decode_cmb.v
decode_cmb2.v
source
decode_cmb.v
示例说明.doc
Example-4-7
sim
work
_info
rev_2
syntmp
clock_edge.prd
clock_edge.prj
clock_edge.v
source
clock_edge.v
syntmp.msg
示例说明.doc
Example-4-4
sim
rev_2
verif
reg_counter.prd
reg_counter.prj
reg_counter.v
source
reg_counter.v
示例说明.doc
Example-4-21
syn_wr
rev_1
oe_edge
rev_2
syntmp
asyn_bad
示例说明.doc
syn_wr
rev_1
Example-4-20
if_single
SynplifyPro
rev_2
if_mult
decode
case
示例说明.doc
if_single
SynplifyPro
Example-4-17
syn_rst
rev_2
syntmp
source
asyn_rst_syn_release
asyn_rst
rev_1
示例说明.doc
syn_rst
Example-4-16
rev_1
verif
source
srl2pal.v
srl2pal.prd
srl2pal.prj
srl2pal.v
示例说明.doc
Example-4-14
clk_div_phase
sim
work
_info
clk_3div
synthesis
rev_1
syntmp
示例说明.doc
Example-4-13
sim
work
_info
ram_basic
rev_2
verif
source
ram_basic.v
示例说明.doc
Example-4-11
rev_1
verif
mux.prd
mux.prj
mux.v
mux2.v
source
mux.v
syntmp.msg
示例说明.doc
Example-4-10
complex_bibus
rev_1
verif
bibus
source
bibus.v
示例说明.doc
Example-4-1
rev_1
syntmp
cnt.prd
cnt.prj
source
cnt1.v
示例说明.doc
Example-3-3
CRC10.v
Example-3-2
FullAdd.v
Example-3-1
FullAdd.v
transcript
Example-2-1
HelloVlog.v