altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TEST...
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VHDL
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资 源 简 介
altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
文 件 列 表
DCT
transcript
simulation
dctsim2
db
dct.bsf
dct.v
dctu.bsf
dctu.v
dctub.bsf
dctub.v
dct_cos_table.v
dct_mac.bsf
dct_mac.v
dct_syn.asm.rpt
dct_syn.bsf
dct_syn.done
dct_syn.dpf
dct_syn.eda.rpt
dct_syn.fit.rpt
dct_syn.fit.smsg
dct_syn.fit.summary
dct_syn.flow.rpt
dct_syn.map.rpt
dct_syn.map.summary
dct_syn.pin
dct_syn.pof
dct_syn.qpf
dct_syn.qsf
dct_syn.qws
dct_syn.sim.rpt
dct_syn.sof
dct_syn.tan.rpt
dct_syn.tan.summary
dct_syn.v
dct_syn.vwf
fdct.bsf
fdct.v
RTL VIEW.doc
zigzag.bsf
zigzag.v
读我.txt
