This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
- 资源大小：2.15 MB
- 上传时间：2021-06-30
- 下载次数：0次
- 浏览次数：1次
- 资源积分：1积分
-
标 签：
VHDL
vhdl
资 源 简 介
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
