时钟分频的 verilog

时钟司程序测试所选定的值 （32 位）。填空 Altera QuartusII Verilog。

clockdiv_teste
incremental_db
compiled_partitions
clockdiv_teste.db_info
simulation
modelsim
clockdiv_teste_modelsim.xrf
greybox_tmp
db
clockdiv_teste.db_info
output_files
clk_div.v
clockdiv_teste.qpf
clockdiv_teste.qsf
clkdiv.png
clk_div.bsf
const1.qip
const1.vhd
const1.cmp
const1.bsf
clockdiv_teste.bdf
clockdiv_teste.qws
const2.qip
contador1.qip
cont1.qip
output_files
clockdiv_teste.map.summary
clockdiv_teste.map.rpt
clockdiv_teste.flow.rpt
clockdiv_teste.pin
clockdiv_teste.fit.smsg
clockdiv_teste.fit.summary
clockdiv_teste.fit.rpt
clockdiv_teste.jdi
clockdiv_teste.sof
clockdiv_teste.pof
clockdiv_teste.asm.rpt
clockdiv_teste.sta.summary
clockdiv_teste.sta.rpt
clockdiv_teste.eda.rpt
clockdiv_teste.done
const1.qip
clockdiv_teste.cdf
greybox_tmp
cbx_args.txt
mg4h8.v
cbx_args.txt