Verilog for lsfr over bist

当设计的记忆与大的部分，其中包括电容对位线。两位线用于执行读和写操作，由于放电电容在写操作中的操作。7T sram 存储单元减少了活性因子的排位线对执行写操作。7T sram 存储单元减少了活性因子的排位线对执行写操作。

bist1
_xmsgs
xst
isim
.lso
alu.cmd_log
alu.lso
alu.prj
alu.stx
alu.syr
alu.v
alu.xst
alu_summary.html
bist1.ise
bist1.ise_ISE_Backup
bist1.ntrc_log
isim.cmd
isim.hdlsourcefiles
isim.log
isim.tmp_save
_1
isimwavedata.xwv
tbw.ant
tbw.jhd
tbw.tbw
tbw.tfw
tbw.xwv
tbw.xwv_bak
tbw_beh.prj
tbw_bencher.prj
tbw_isim_beh.exe
test.ant
test.jhd
test.tbw
test.xwv
test.xwv_bak
test1.ant
test1.jhd
test1.tbw
test1.tfw
test1.xwv
test1.xwv_bak
test12.ant
test12.jhd
test12.tbw
test12.tfw
test12.xwv
test12.xwv_bak
test123.ant
test123.jhd
test123.tbw
test123.tfw
test123.xwv
test123.xwv_bak
test123_beh.prj
test123_bencher.prj
test123_isim_beh.exe
test12_bencher.prj
test1_beh.prj
test1_bencher.prj
test1_isim_beh.exe
test_beh.prj
test_bencher.prj
test_isim_beh.exe
xilinxsim.ini
__ISE_repository_bist1.ise_.lock
isim.tmp_save