verilog fifo 代码

FIFO is a First-In-First-Out memory queue with control logic that manages  the read and write operations, generates status flags, and provides optional  handshake signals for interfacing with the user logic. It is often used to  control the flow of data between source and destination. FIFO can be  classified as synchronous or asynchronous depending on whether same clock  or different (asynchronous) clocks control the read and write operations. In  this project the objective is to design, verify and synthesize a synchronous  FIFO using binary coded read and write pointers to address the memory  array. FFIO full and empty flags are generated and passed on to source and  destination logics, respectively, to pre-empt any overflow or underflow of  data. In this way data integrity between source and destination is maintained.  The RTL description for the FIFO is

RW_sync_fifo
_xmsgs
isim
iseconfig
ipcore_dir
FIFO_design.pdf
fuse.log
fuse.xmsgs
fuseRelaunch.cmd
isim.cmd
mem_array.v
mem_array_stx_beh.prj
read_control_logic.v
read_control_logic_stx_beh.prj
RW_sync_fifo.gise
RW_sync_fifo.xise
sync_fifo.v
sync_fifo_stx_beh.prj
sync_fifo_summary.html
sync_fifo_tb.v
sync_fifo_tb_beh.prj
sync_fifo_tb_isim_beh.exe
sync_fifo_tb_isim_beh1.wdb
sync_fifo_tb_stx_beh.prj
write_control_logic_stx_beh.prj
write_control_logoc.v
xilinxsim.ini