计数器，vhdl，调试通过。

COUNTER 用于xilinx硬件，里面已建工程，修改ucf即可。设计由3部分组成，计数器，100M分配时钟，顶层模块，其中顶层模块包括计数器和分频器。

counter_VHDL
_xmsgs
iseconfig
ipcore_dir
.Xil-PlanAhead-4000-hebin
ngc2edif
ngc2edif.log
201110171347.cfi
201110171347.mcs
201110171347.prm
BPI_DATA.cfi
BPI_DATA.mcs
BPI_DATA.prm
counter.gise
counter.xise
counter3b.vhd
counter3b_summary.html
div_clk.cmd_log
div_clk.lso
div_clk.vhd
fuse.xmsgs
fuseRelaunch.cmd
pa.fromNcd.tcl
pa.fromNetlist.tcl
par_usage_statistics.html
pepExtractor.prj
planAhead.ngc2edif.log
SPI_DATA.cfi
SPI_DATA.exo
SPI_DATA.mcs
SPI_DATA.prm
test_counter.vhd
top.fdo
top.msd
top.rbb
top.rbd
top.ucf
top.udo
top.vhd
top.xdl
top_bitgen.xwbt
top_guide.ncd
top_xpa.log
top_xpwr.log
webtalk_power.xml
.Xil-PlanAhead-4000-hebin