arm9内核的verilog实现

采用verilog hdl语言写的一个完整的arm9架构软核处理器，可以综合，对于处理器软核设计开发具有很大的参考价值，可移植到xlinx，altera等fpga芯片平台上。

arm9_fpga2_verilog
README
pardef
align.v
alu.v
arm9.v
clock_if_entarch.vhd
clock_io_entarch.vhd
comp42_2.v
comp42_n40.v
comp42_n64.v
control.v
counters.v
dcache.v
decode.v
dtag.v
dtag_synth.v
ex.v
host.vhd
host_dcomp.vhd
host_icomp.vhd
icache.v
id.v
ifetch.v
interlock.v
io_conn_if_entarch.vhd
itag.v
itag_synth.v
lad_bus_if_entarch.vhd
lad_bus_io_entarch.vhd
lec25dscc25.v
led_if_entarch.vhd
led_io_entarch.vhd
mainmem.v
mapreg.v
mapspsr.v
me.v
mem_copy.c
mem_if_entarch.vhd
mem_init.dat
mem_io_entarch.vhd
mezz_mem_card_cfg.vhd
miniram.v
mmu_new.v
modelsim.ini
mult.v
multacc.v
pardef.v
pe0_bus_if_entarch.vhd
pe0_bus_io_entarch.vhd
pex.fes
pex.ucf
pex.vhd
pex_ent.vhd
pex_mezz_mem_if_entarch.vhd
pex_mezz_mem_io_entarch.vhd
pex_synth.vhd
pe_arm2mem_if_entarch.vhd
pe_lad2mem_if_entarch.vhd
pe_mezz_mem_pkg.vhd
pe_pkg.vhd
pipe.v
ppselect.v
project_vcom.do
project_vsim.do
ram1p.v
ram1p_synth.v
ram2p.v
ram2p_synth.v
regfile.v
shifter.v
system_cfg.vhd
systolic_if_entarch.vhd
systolic_io_entarch.vhd
tag.v
testarm.vhx
vlog.opt
wave.do
xilinx_pkg.vhd
www.pudn.com.txt