资 源 简 介
The challenges associated with the design and implementation of Electro-
static Discharge (ESD) protection circuits become increasingly complex as
technology is scaled well into nano-metric regime. One must understand the
behavior of semiconductor devices under very high current densities, high
temperature transients in order to surmount the nano-meter ESD challenge.
As a consequence, the quest for suitable ESD solution in a given technology
must start from the device level. Traditional approaches of ESD design may
not be adequate as the ESD damages occur at successively lower voltages in
nano-metric dimensions.
