资 源 简 介
An interactive simulator for digital combinational and sequential logic. The project aims to create a verificative and educational tool with an intuitive and responsive user interface.
A user of the finished software can construct a logic circuit by selecting components from a library and then connect them together in permissible ways whilst logical and aesthetic design rules are enforced. These circuits can then be stored to disk for later modification or simulated and logged over time to produce a graphical representation of the state of the circuit at user chosen locations. The application can be easily extended with custom component libraries, and user created sub-circuits.
The software is written in Java(TM) and was developed as a 3rd Year Project by two undergraduate Computer Science students from Worcester College, Oxford, UK in 2009.
Their individual project reports are included in the download section for prosperity.
Currently the project is not being active
